In recent years, with the development of semiconductor IC fabrication technology, the number of components in a single chip has been increasing, and the size of such components has been shrinking due to increasingly higher integration, compressing the IC line width to the order of micrometers. However, no matter how the component size is reduced, individual components in a single chip must be properly insulated or isolated from one another, in order for good properties of the components to be achieved. This is usually accomplished by a so-called component isolation technique which aims essentially to form isolations between individual components, which ensures a desired isolation effect while having a minimized footprint so as to leave more chip real estate such that a greater number of components can be accommodated.
In the semiconductor fabrication technology of the state of the art, a silicon-on-insulator (SOI) technique is often employed to achieve a good isolation. This technique allows effective improvements in body effects resulting from feature size reductions of semiconductor devices. Alternatively, insulating silicon islands formed in predetermined regions by depositing and polishing polysilicon and then flipping over the substrate can provide a complete isolation. Both of these techniques are associated with a high process complexity, a high cost and a long manufacturing cycle.
FIGS. 1 to 4 are schematics illustrating individual steps in a method for fabricating a silicon island structure. As shown in figures, the method includes:
at first, providing a silicon substrate 10, forming a plurality of trenches 11 therein and depositing an oxide layer 12 which covers sidewalls and bottoms of the trenches 11 as well as the silicon substrate 10, resulting in a structure as shown in FIG. 1;
subsequently, depositing a polysilicon layer 13 that covers the silicon substrate 10 and fills the trenches 11, as shown in FIG. 2;
after that, planarizing the surface of the polysilicon layer 13 by chemical mechanical polishing (CMP), as shown in FIG. 3; and
at last, flipping over the silicon substrate 10 and performing a CMP process on the side of the silicon substrate 10 that has not been processed until the oxide layer 12 is exposed. As a result, in the remainder of the silicon substrate 10, there is a plurality of silicon islands 14 that are completely isolated from one another by the trenches 11, as shown in FIG. 4.
However, this method involves two CMP processes (respectively on the polysilicon layer 13 and on the flipped silicon substrate 10) which are subject to accuracy limitations and are associated with low uniformity controllability. In particular, in the second CMP process subsequent to the flipping of the silicon substrate 10, it tends to occur that part of the oxide layer 12 is exposed or even removed, with the remainder of the oxide layer still being buried beneath the silicon substrate, which will impose an adverse impact on the performance of the formed silicon islands. Moreover, after the silicon islands 14 are formed, in order to provide the silicon substrate with a support, it is further required to bond a carrier substrate to its bottom side (i.e., the side closer to the silicon islands 14). This bonding step, coupled with the two CMP processes, makes the conventional method suffer from a high process complexity, a high cost and a long manufacturing cycle.
On the other hand, the SOI technique usually involves an ion implantation or a substrate bonding, which also lead to a high process complexity, a high cost and a long manufacturing cycle.